《模擬電子線路》全套PPT課件

《模擬電子線路》全套PPT課件,模擬電子線路,模擬,電子線路,全套,PPT,課件 第五章第五章集成運算放大電路集成運算放大電路 1集成電路集成電路：60年代發(fā)展起來的一種新型器件，把眾多年代發(fā)展起來的一種新型器件，把眾多晶體管、電阻、電容及連線制作在一塊半導(dǎo)體芯片晶體管、電阻、電容及連線制作在一塊半導(dǎo)體芯片（如：硅片）上，做成具有特定功能的獨立電子線路。（如：硅片）上，做成具有特定功能的獨立電子線路。外型一般用金屬圓殼或雙列直插結(jié)構(gòu)。外型一般用金屬圓殼或雙列直插結(jié)構(gòu)。集成電路具有性能好，可靠性高，體積小，集成電路具有性能好，可靠性高，體積小，耗耗電少，成本低等優(yōu)點。電少，成本低等優(yōu)點。2Jack Kilby的第一塊集成電路的第一塊集成電路 34采用采用65納米工藝制造，內(nèi)部集成納米工藝制造，內(nèi)部集成2.91億個晶體管億個晶體管5集成運放：集成運放：是一是一 種種模擬集成電路模擬集成電路，早期實現(xiàn)各種，早期實現(xiàn)各種數(shù)學(xué)運算，主要用于模擬計算機(jī)；現(xiàn)在廣泛應(yīng)用數(shù)學(xué)運算，主要用于模擬計算機(jī)；現(xiàn)在廣泛應(yīng)用于各種電子系統(tǒng)中。于各種電子系統(tǒng)中。65.1 集成運算放大器的特點集成運算放大器的特點1.級間采用直接耦合方式級間采用直接耦合方式(集成工藝不能制作集成工藝不能制作大電容和電感大電容和電感)；2.盡可能采用有源器件代替無源器件盡可能采用有源器件代替無源器件(避免使避免使用大電容、大電阻用大電容、大電阻)；3.利用對稱結(jié)構(gòu)改善電路性能利用對稱結(jié)構(gòu)改善電路性能(采用對稱結(jié)構(gòu)采用對稱結(jié)構(gòu)的差動放大器，抑制工作點漂移，解決零漂現(xiàn)象的差動放大器，抑制工作點漂移，解決零漂現(xiàn)象)。7 圖圖5.1.1 集成運算放大器組成框圖集成運算放大器組成框圖 差動差動放大器放大器負(fù)載為有源負(fù)載為有源負(fù)載的共射負(fù)載的共射放大器放大器射隨器或射隨器或互補(bǔ)射隨器互補(bǔ)射隨器85.2 電流源電路電流源電路1、為各級電路提供穩(wěn)定的直流偏置電流、為各級電路提供穩(wěn)定的直流偏置電流2、可作為有源負(fù)載代替集電極電阻、可作為有源負(fù)載代替集電極電阻RC。電流源的作用：電流源的作用：9 單管電流源電路單管電流源電路 IC0IBUCER1R2ICR3UEEICRo(a)晶體管的恒流特性晶體管的恒流特性(b)電電流源電路流源電路(c)等效電流等效電流源表示法源表示法10圖圖5.2.1 鏡像電流源鏡像電流源 一、鏡像電流源一、鏡像電流源11圖圖5.2.2 多路鏡像電流源多路鏡像電流源12IrRrIC1IC2UCCIC3RrIrIC2IC3V3V2V1UCC圖圖5.3.2 多集電極晶體管鏡像電流源多集電極晶體管鏡像電流源(a)三集電極橫向三集電極橫向PNP管電路管電路(b)等價電路等價電路集成電路中多路鏡像電流源的實現(xiàn)集成電路中多路鏡像電流源的實現(xiàn)13二、比例電流源二、比例電流源 圖圖5.2.4 比例電流源比例電流源14若若1，則，則 IE1Ir,IE2IC215三、微電流電流源三、微電流電流源RrIrIC2V2V1UCCR2圖圖5.2.5 微電流電流源微電流電流源當(dāng)當(dāng) 11時時，IE1Ir,IE2IC2已已知知Ir=1mA,要求要求IC2=10A時時16 四、威爾遜電流源四、威爾遜電流源圖圖5.2.6 威爾遜電流源威爾遜電流源 17 若三管特性相同，則若三管特性相同，則1=2=3=,18當(dāng)環(huán)境改變（如溫度升高）當(dāng)環(huán)境改變（如溫度升高）IC3IE3IC2IC1(Ir固定固定)IB3IC319六、有源負(fù)載放大器六、有源負(fù)載放大器 UCCV3V2uoV1uiRr圖圖5.3.1 有源負(fù)載放大器有源負(fù)載放大器(a)共射電路共射電路(b)等效電路等效電路20圖圖5.3.1 有源負(fù)載放大器有源負(fù)載放大器(b)等效電路等效電路(b)交流小信號等效電路交流小信號等效電路215.4 差動放大電路差動放大電路5.4.1 零點漂移現(xiàn)象零點漂移現(xiàn)象圖圖 5.4.1 零點漂移現(xiàn)象零點漂移現(xiàn)象（a）測試電路）測試電路 （b）輸出電壓的漂移）輸出電壓的漂移22零點漂移現(xiàn)象零點漂移現(xiàn)象1.靜態(tài)時，由于溫度變化，電源波動等因素靜態(tài)時，由于溫度變化，電源波動等因素的影響，會使工作點電壓的影響，會使工作點電壓(即集電極電位即集電極電位)偏離設(shè)偏離設(shè)定值而緩慢地上下飄動。定值而緩慢地上下飄動。2.對直接耦合放大電路，這種飄動會逐級放對直接耦合放大電路，這種飄動會逐級放大，會使后級放大器進(jìn)入截止區(qū)和飽和區(qū)，大，會使后級放大器進(jìn)入截止區(qū)和飽和區(qū)，這樣這樣整個電路將無法正常工作。整個電路將無法正常工作。3.差動放大器電路能有效地克服零點漂移。差動放大器電路能有效地克服零點漂移。23抑制零點漂移現(xiàn)象的措施：抑制零點漂移現(xiàn)象的措施：（1）電路中引入直流負(fù)反饋，穩(wěn)定靜態(tài)工作）電路中引入直流負(fù)反饋，穩(wěn)定靜態(tài)工作點，減小零漂。點，減小零漂。（2）利利用用熱熱敏敏元元件件對對放放大大管管進(jìn)進(jìn)行行溫溫度度補(bǔ)補(bǔ)償償。（3）采用）采用“差動放大電路差動放大電路”。245.4.2 差動放大器的工作原理及性能分析差動放大器的工作原理及性能分析一一、電路形成原理、電路形成原理圖圖 5.4.2 差動放大電路的形成差動放大電路的形成25圖圖 5.4.2 差動放大電路的形成差動放大電路的形成26UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo 圖圖5.4.2 基本差動放大器基本差動放大器當(dāng)當(dāng)Ui1=Ui2=0時時則流過則流過RE的電流的電流I為為故有故有二、差動放大電路的靜態(tài)分析二、差動放大電路的靜態(tài)分析27UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo 圖圖5.4.2 基本差動放大器基本差動放大器靜態(tài)時，差動放大靜態(tài)時，差動放大器兩輸出端之間的器兩輸出端之間的直流電壓為零。直流電壓為零。（a）雙端輸出雙端輸出28 圖圖5.4.2 基本差動放大器基本差動放大器（b）單端輸出單端輸出IBQ1=IBQ2 ICQ1=ICQ2 UCEQ2UCC+0.7-ICQ1RC UCEQ1-UCQ1+0.7 29二、差動放大電路的動態(tài)分析二、差動放大電路的動態(tài)分析UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo共模信號共模信號:Ui1和和Ui2所加的信號所加的信號大小相等大小相等,極性相同極性相同 Ib1=Ib2，Ic1=Ic2 Uc1=Uc2 輸出電壓輸出電壓Uo=0 30UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo差模信號差模信號:Ui1和和Ui2所加的信號所加的信號大小相等大小相等,極性相反極性相反 Uc1=Uc2 Uo=Uc1 Uc2 =2 Uc1 311、共模抑制特性、共模抑制特性UCCRCUC2RLRCUC1Ui2REUEEV1V2UoUic1Uic2Ui1UiC2REUEE2REUEE32雙端輸出時，負(fù)載雙端輸出時，負(fù)載RL上的電流為零，相當(dāng)于上的電流為零，相當(dāng)于RL開路開路 每個管子的射極相當(dāng)于各接有每個管子的射極相當(dāng)于各接有2RE的電阻的電阻 RCUoc2RCUoc1UicV1V2Uoc2RE圖圖5.4.4 基本差動放大器的共模等效通路基本差動放大器的共模等效通路 R2E331.共模電壓放大倍數(shù)共模電壓放大倍數(shù)Auc雙端輸出時的共模電壓放大倍數(shù)雙端輸出時的共模電壓放大倍數(shù)RCUoc2RCUoc1UicV1V2Uoc2RER2E34差動電路能夠克服零點漂移現(xiàn)象的根本原因：差動電路能夠克服零點漂移現(xiàn)象的根本原因：共模信號一般指由于外界影響（共模信號一般指由于外界影響（，T，UCC），引起工作點的漂移，折算到輸入端就是一種共），引起工作點的漂移，折算到輸入端就是一種共模信號，雙端輸出時，只要對稱性好，則模信號，雙端輸出時，只要對稱性好，則UOC=0，可以完全抑制外界的干擾。單端輸出時，由于可以完全抑制外界的干擾。單端輸出時，由于RE的的調(diào)節(jié)作用使輸出大為減少。調(diào)節(jié)作用使輸出大為減少。RCUoc2RCUoc1UicV1V2Uoc2RER2E35 2.共模輸入電阻共模輸入電阻 3.共模輸出電阻共模輸出電阻 雙端輸出時為雙端輸出時為 單端輸出時為單端輸出時為 RCUoc2RCUoc1UicV1V2Uoc2RER2E36共模電壓放大倍數(shù)共模電壓放大倍數(shù)通通常常滿滿足足(1+)2RErbe，所以又可簡化為所以又可簡化為圖圖 5.4.5 單端輸出單端輸出37通通常常滿滿足足(1+)2RErbe，所以又可簡化為所以又可簡化為圖圖 5.4.5 單端輸出單端輸出結(jié)論：結(jié)論：由于射極電阻由于射極電阻2RE的存在，使單端的存在，使單端輸出時的共模電壓放輸出時的共模電壓放大總倍數(shù)大為減小。大總倍數(shù)大為減小。即差動放大器對共模即差動放大器對共模信號不是放大而是抑信號不是放大而是抑制，且制，且RE抑制作用抑制作用越強(qiáng)。越強(qiáng)。38UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo2、差模放大特性、差模放大特性Uid1Uid2Uid=Uid1-Uid2RE上只有靜態(tài)電壓，而不產(chǎn)生差模信號電壓。上只有靜態(tài)電壓，而不產(chǎn)生差模信號電壓。雙端輸出時，負(fù)載雙端輸出時，負(fù)載RL的中點電位為的中點電位為0。39圖圖5.4.6 基本差動放大器的差模等效通路基本差動放大器的差模等效通路Uod1Uod2RL2RL2V2V1Uid1Uid2Uid=Uid1-Uid2RCRCUod40 1.差模電壓放大倍數(shù)差模電壓放大倍數(shù)在雙端輸出時在雙端輸出時Uod1Uod2RL2RL2V2V1Uid1Uid2RCRC41所以所以 式中：式中：結(jié)論：結(jié)論：雙端輸出時的差模電壓放大倍數(shù)等于單雙端輸出時的差模電壓放大倍數(shù)等于單邊共射放大器的電壓放大倍數(shù)。邊共射放大器的電壓放大倍數(shù)。Uod1Uod2RL2RL2V2V1Uid1Uid2RCRC42UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo單端輸出時單端輸出時:信號只從一端輸出。信號只從一端輸出。43或或RCUC2RLRCUC1Ui1Ui2REV1V2Uod1Uid=Uid1-Uid2式中：式中：44結(jié)論：結(jié)論：單端輸出時的差模電壓放大倍數(shù)為單單端輸出時的差模電壓放大倍數(shù)為單邊共射電路電壓放大倍數(shù)的一半，且兩輸出邊共射電路電壓放大倍數(shù)的一半，且兩輸出端信號的相位相反。端信號的相位相反。RCUC2RLRCUC1Ui1Ui2REV1V2UodUod1Uod2RL2RL2V2V1Uid1Uid2RCRC452.差模輸入電阻差模輸入電阻Uod1Uod2RL2RL2V2V1RCRCUodUid1Uid2Iid46Uod1Uod2RL2RL2V2V1RCRCUodUid1Uid2Iid 3.差模輸出電阻差模輸出電阻雙端輸出時為雙端輸出時為單端輸出時為單端輸出時為47三、共模抑制比三、共模抑制比KCMR差模：需要放大的有用信號，盡可能的放大。差模：需要放大的有用信號，盡可能的放大。共模：無用的干擾信號，需要抑制。共模：無用的干擾信號，需要抑制。為了衡量差動放大電路對差模信號的放大和對共為了衡量差動放大電路對差模信號的放大和對共模信號的抑制能力，通常用模信號的抑制能力，通常用共模抑制比共模抑制比來衡量。來衡量。48KCMR實質(zhì)上是反映實際差動電路的對稱性。實質(zhì)上是反映實際差動電路的對稱性。理想情況下：在理想情況下：在雙端雙端輸出理想對稱的情況下，輸出理想對稱的情況下，Auc=0，KCMR。為了定量分析，通常用為了定量分析，通常用單端單端輸出的輸出的KCMR。49四、對任意輸入信號的放大特性四、對任意輸入信號的放大特性UCCRCUC2RLRCUC1Ui1Ui2REUEEV1V2Uo5051UCCRCUC2RLRCUC1REUEEV1V2Uo5253在實際應(yīng)用中，當(dāng)在實際應(yīng)用中，當(dāng)只有一路只有一路信號源接到差動信號源接到差動放大器的兩個輸入端時：放大器的兩個輸入端時：如兩端都不接地，這種接法稱為如兩端都不接地，這種接法稱為雙端輸入雙端輸入；如信號源一端接地，這種接法稱為如信號源一端接地，這種接法稱為單端輸入單端輸入。54差放特性的幾點結(jié)論：差放特性的幾點結(jié)論：1、差動放大電路的性能只與輸出端的接法有關(guān)，與輸入、差動放大電路的性能只與輸出端的接法有關(guān)，與輸入端的接法無關(guān)；端的接法無關(guān)；RCUC2RLRCUC1Ui1Ui2REV1V2UodUod1Uod2RL2RL2V2V1Uid1Uid2RCRC552、雙端輸出雙端輸出的差模電壓放大倍數(shù)等于半邊差模等效電路的差模電壓放大倍數(shù)等于半邊差模等效電路的電壓放大倍數(shù)，即與單管共射放大電路相同。的電壓放大倍數(shù)，即與單管共射放大電路相同。單端輸出單端輸出差模電壓放大倍數(shù)僅是半邊差模等效電路電壓放大倍數(shù)的差模電壓放大倍數(shù)僅是半邊差模等效電路電壓放大倍數(shù)的一半；一半；RCUC2RLRCUC1Ui1Ui2REV1V2UodUod1Uod2RL2RL2V2V1Uid1Uid2RCRC563、雙端輸出雙端輸出的輸出電阻為的輸出電阻為2RC，單端輸出單端輸出的輸出電阻僅是的輸出電阻僅是雙端輸出的一半；雙端輸出的一半；4、無論是雙端輸入還是單端輸入，差模輸入電阻均等于、無論是雙端輸入還是單端輸入，差模輸入電阻均等于半邊差模等效電路輸入電阻的兩倍。共模輸入電阻遠(yuǎn)大于半邊差模等效電路輸入電阻的兩倍。共模輸入電阻遠(yuǎn)大于差模輸入電阻。差模輸入電阻。RCUC2RLRCUC1Ui1Ui2REV1V2UodUod1Uod2RL2RL2V2V1Uid1Uid2RCRC575.4.3 具有電流源的差動放大電路具有電流源的差動放大電路 在差動放大電路中，特別是在單端輸在差動放大電路中，特別是在單端輸出電路中，我們希望發(fā)射極電阻出電路中，我們希望發(fā)射極電阻RE的阻值的阻值越大越好，這樣可以有效地抑制工作點漂越大越好，這樣可以有效地抑制工作點漂移，提高共模抑制比。移，提高共模抑制比。58UCCRCUC2RLRCUC1Ui1Ui2RE UEEV1V2Uo增大增大RE流流過過RE的的電電流流I減小減小每管的靜每管的靜態(tài)態(tài)集集電電極極電電流流IEQ減小減小保持電源電壓保持電源電壓UEE不變不變59UCCRCUC2RLRCUC1Ui1Ui2RE UEEV1V2Uo增大增大RE造成電源造成電源UEE過大過大 保持電流保持電流I不變不變 60RCRCUi1V1V2UoUi2 UEEIUCCRCUC2RCUC1Ui1V1V2Uoc UEEV3UB3R1R2R3Ui2UCC圖圖5.4.9 具有電流源的差動放大器電路具有電流源的差動放大器電路(a)用單管電流源代替用單管電流源代替RE的差動電的差動電路路(b)電路的簡化表示電路的簡化表示恒流源恒流源61靜態(tài)工作點的估算：靜態(tài)工作點的估算：RCUC2RCUC1Ui1V1V2Uoc UEEV3UB3R1R2R3Ui2UCC62圖圖 5.4.10 場效應(yīng)管差動放大電路場效應(yīng)管差動放大電路63上述章節(jié)討論的電壓增益往往是小信號情上述章節(jié)討論的電壓增益往往是小信號情況下的分析，在大信號情況下，差動電路的工作況下的分析，在大信號情況下，差動電路的工作情況又如何？情況又如何？5.4.4 差動放大器的大信號分析差動放大器的大信號分析64圖圖5.4.11 簡化的差動放大器簡化的差動放大器RCRCuidV1V2uo UEEIUCCiC2iC1一、一、傳輸特性傳輸特性 定義定義：差動放大器輸出電流或輸出電壓與：差動放大器輸出電流或輸出電壓與差模差模輸入輸入電壓之間的函數(shù)關(guān)系。電壓之間的函數(shù)關(guān)系。65圖圖5.4.11 簡化的差動放大器簡化的差動放大器RCRCuidV1V2uo UEEIUCCiC2iC166電流傳輸特性電流傳輸特性67電壓傳輸特性電壓傳輸特性68iC1,iC2IiC1iC2iC1iC26 UT/4 UT2 UT02UT4UT6UTuidQI2(a)電流傳輸特性曲線電流傳輸特性曲線69(b)電壓傳輸特性曲線電壓傳輸特性曲線 圖圖5.4.12 差動放大器的傳輸特性曲線差動放大器的傳輸特性曲線uoIRC6UT/4UT2UT02UT4UT6UTuid IRC70兩管集電極電流之和恒等于兩管集電極電流之和恒等于I傳輸特性具有非線性特性傳輸特性具有非線性特性當(dāng)當(dāng)uid=0時，差動電路處于靜態(tài)，這時時，差動電路處于靜態(tài)，這時iC1=iC2=ICQ=I/21.在靜態(tài)工作點附近，當(dāng)在靜態(tài)工作點附近，當(dāng)|uid|UT，即室溫下，即室溫下，uid在在26mV以內(nèi)時，以內(nèi)時，傳輸特性近似為一段直線傳輸特性近似為一段直線。2.當(dāng)當(dāng)|uid|4 UT,即即uid超過超過100mV時，傳輸特性明時，傳輸特性明顯彎曲，而后趨于水平。顯彎曲，而后趨于水平。71(RB)(RB)V1V2RRUEEI(a)串接串接R(RB)的線性區(qū)擴(kuò)展電路的線性區(qū)擴(kuò)展電路 圖圖5.4.13 擴(kuò)展差動電路的線性區(qū)范圍擴(kuò)展差動電路的線性區(qū)范圍72iC1,iC2II/2R(RB)0uid 圖圖5.4.13 擴(kuò)展差動電路的線性區(qū)范圍擴(kuò)展差動電路的線性區(qū)范圍(b)線性區(qū)擴(kuò)展后的電流傳輸特性曲線線性區(qū)擴(kuò)展后的電流傳輸特性曲線 73二、二、差動放大電路正常工作的前提條件差動放大電路正常工作的前提條件1.差放電路輸入電壓的幅值是有限制的差放電路輸入電壓的幅值是有限制的差模差模輸入電壓輸入電壓所受的限制所受的限制74共模輸入電壓所受的限制共模輸入電壓所受的限制 當(dāng)共模輸入電壓為正，當(dāng)共模輸入電壓為正，且超過差分對管的集電極電且超過差分對管的集電極電壓時，則差分對管進(jìn)入飽和壓時，則差分對管進(jìn)入飽和區(qū)；區(qū)；當(dāng)共模輸入電壓為負(fù)，當(dāng)共模輸入電壓為負(fù)，且負(fù)電壓低于電流源晶體管且負(fù)電壓低于電流源晶體管的基極電位，電流管進(jìn)入飽的基極電位，電流管進(jìn)入飽和區(qū)。即共模輸入電壓應(yīng)滿和區(qū)。即共模輸入電壓應(yīng)滿足足UB3uic UC1RCUC2RCUC1Ui1V1V2Uoc UEEV3UB3R1R2R3Ui2UCC752.電流源電流電流源電流I小于差放管的集電極臨界飽和電流小于差放管的集電極臨界飽和電流ICS(臨界臨界)兩差放管的靜態(tài)工作兩差放管的靜態(tài)工作點應(yīng)該設(shè)置在交流負(fù)點應(yīng)該設(shè)置在交流負(fù)載線（由于差放電路載線（由于差放電路是直接耦合，交、直是直接耦合，交、直流負(fù)載線重合）中點流負(fù)載線重合）中點偏低的位置，即偏低的位置，即ICQIEQ ICS(臨界臨界)/2 76三、差動放大電路作模擬乘法器三、差動放大電路作模擬乘法器uid2UT50mV 77785.4.5 差動放大器的失調(diào)及溫漂差動放大器的失調(diào)及溫漂一、差動放大器的失調(diào)一、差動放大器的失調(diào)當(dāng)輸入信號為零時，由于兩晶體管參數(shù)和電當(dāng)輸入信號為零時，由于兩晶體管參數(shù)和電阻值不可能做到完全對稱，因而使得輸出不為零。阻值不可能做到完全對稱，因而使得輸出不為零。這種現(xiàn)象，稱為這種現(xiàn)象，稱為差動放大器的失調(diào)差動放大器的失調(diào)。輸入失調(diào)電壓輸入失調(diào)電壓UIO 輸入失調(diào)電流輸入失調(diào)電流 IIO。補(bǔ)償方法：人為的在輸入端加補(bǔ)償電壓或電補(bǔ)償方法：人為的在輸入端加補(bǔ)償電壓或電流，流，79圖圖 5.4.16 差放的輸入失調(diào)電壓和輸入失調(diào)電流差放的輸入失調(diào)電壓和輸入失調(diào)電流令令 1=，2=+80圖圖 5.4.17 差動放大電路的調(diào)零電路差動放大電路的調(diào)零電路射極調(diào)零射極調(diào)零集電極調(diào)零集電極調(diào)零81 射極調(diào)零電路的差動放大器的差模增射極調(diào)零電路的差動放大器的差模增益和輸入電阻為：益和輸入電阻為：82 二、失調(diào)的溫度漂移二、失調(diào)的溫度漂移調(diào)零電路可在某一特定溫度下，使輸出為調(diào)零電路可在某一特定溫度下，使輸出為0。但失調(diào)會隨著溫度的改變而發(fā)生變化，所以。但失調(diào)會隨著溫度的改變而發(fā)生變化，所以仍存在零點的仍存在零點的溫度漂移現(xiàn)象溫度漂移現(xiàn)象。調(diào)零電路可以克服失調(diào)，但不能克服溫漂。調(diào)零電路可以克服失調(diào)，但不能克服溫漂。83UIO的溫漂與該溫度下的的溫漂與該溫度下的UIO的大小成正比。的大小成正比。84IIO的溫漂主要取決于的溫漂主要取決于的溫度系數(shù)和的溫度系數(shù)和IIO本身。本身。85IC=IC1+IC2 =1 IB+2(1+1)IB =1+2(1+1)IB 用兩只同類型的雙極型用兩只同類型的雙極型晶體管按圖形式連接，即一晶體管按圖形式連接，即一組電極并聯(lián)，一組電極串聯(lián)，組電極并聯(lián)，一組電極串聯(lián)，兩只晶體管的電流符合電流兩只晶體管的電流符合電流流通方向，便組成一個三端流通方向，便組成一個三端等效復(fù)合器件。等效復(fù)合器件。通常把這種雙管復(fù)合器通常把這種雙管復(fù)合器件稱為達(dá)林頓復(fù)合管或達(dá)林件稱為達(dá)林頓復(fù)合管或達(dá)林頓對。頓對。=IC/IB =1+2(1+1)1 2 ICIBIE 1 2 IC1IC2IB25.5 復(fù)合管及其放大電路復(fù)合管及其放大電路8687電流放大倍數(shù)電流放大倍數(shù) Ai=1 2 輸入電阻輸入電阻若忽略若忽略rbb 得得 88Ro=RC 895.6 集成運算放大器的輸出級電路集成運算放大器的輸出級電路RL NA,bvSince XB Ln in the base,most of the injected electrons get to the collector without recombining with holes.Any holes that do recombine with electrons in the base are supplied as base current.vElectrons reaching the collector are collected across the base-collector depletion region.vSince most of the injected electrons reach the collector and only a few holes are injected into the emitter,or recombine with electrons in the base,IB IC,implying that the device has a large current gain.R.W.KnepperSC412,slide 8-7184vShown at left are the effects of different NPN bias conditions on the energy bands and the electron concentrations:(a)No bias(thermal equilibrium)Fermi levels are flatElectron concentration is ND in emitter and collector and ni2/NA in the base(b)both junctions reverse biasedIncreased E-B&B-C barriersIncrease in depletion regionsElectron density in base=0(c)both junctions forward biasedReduced barrier heightsElectrons injected into base from both emitter and collector(d)forward-biased emitter,reverse-biased collectorSmall E-B/large C-B barriersElectrons injected from emitterElectron density=0 at C-B junction and appears linear in base region(small WB)R.W.Knepper,SC412,slide 8-8185BJT Regions of Operation:Ebers-Moll DC ModelvJim Ebers and John Moll developed a dc model for the bipolar transistor which describes the four regions of operation on the Vbe vs Vbc voltage plot shown at the leftForward active region:vEmitter-base forward biased,collector-base reverse biasedvNormal useful region for BJTvCurrent Gain =100 typicallyReverse active region:vCollector-base forward biased,emitter-base reverse biasedvTransistor is being operated in the inverse modevInverse is usually small 1 or 1Saturation region:vBoth E-B and C-B forward biasedvBase region is flooded with electronsCut-off region:vBoth junction reverse biasedvNo current flowR.W.KnepperSC412,slide 8-9(a)Both junctions are forward-biased the same amount.No current flows even though the base is loaded with charge(electrons).(b)Saturation condition:both junctions forward biased.Net electron flow from emitter to collector.186Ebers-Moll BJT DC Model Current EquationsvThe Ebers-Moll model may be used under all junction bias conditions(i.e.,forward-active,inverse,saturation,and cut-off)to estimate the terminal currents.R.W.KnepperSC412,slide 8-10187Bipolar Transistor Collector CharacteristicsvShown below is a set of BJT(bipolar junction transistor)collector characteristics IC versus VCE with IB as the parametervThe curves have several regions of operationAt low VCE both the emitter-base junction and the collector-base junction are forward-biased,resulting in what is called saturation in the bipolar transistorvThe base volume is flooded with mobile carriers injected from both E-B and C-B junctionsAt higher(normal)VCE only the emitter-base junction is forward-biased,while the collector-base junction is reverse-biased,resulting in the normal active(forward mode)regionvThe carrier concentration is pinned at zero(i.e.very small)at the collector junction,resulting in a linear(triangular)distribution of charge in the basevNon-zero slope in normal active region is caused by base width narrowing due to increase in VCB reverse bias and corresponding increase in C-B depletion region(Early Effect named after Jim Early)At even higher VCE the transistor enters the onset of avalanche breakdown at the CB junctionR.W.KnepperSC412,slide 8-11The non-zero slope in the forward moderegion is modeled,as shown below,witha linear term VCE/VA,where VA is theEarly Voltage.188NPN DC Characteristics vTop left figure shows a set of collector characteristics(common emitter)for base current stepped from 0 to 30 uA for a SiGe HBT with emitter area of 0.5 x 2.5 umVery flat curves indicate Early voltage greater than 70 volts.vGummel plots showing log Ic and log Ib versus VBE indicate excellent SiGe NPN behavior and extremely low recombination current at low VBEBeta remains constant at about 200 to VBE=0.9 volt or higherR.W.KnepperSC412,slide 8-12Harame,et al.,IEEE Trans ED,Vol.48,No.11,Nov.2001189Definitions of fT and fmaxvCuttoff frequency fT can be defined as a series of time constants including base storage time b,emitter storage time e,collector storage time c,and several RC time constants due to emitter and collector depletion capacitances and collector-to-substrate capacitanceR.W.KnepperSC412,slide 8-13IBM SiGe Design Kit Training:Technology,IBM Microelectronics,Burlington,VT,July 2002Normally the dominant terms in order of significance are the base storage time b,emitter storage time e,and the depletion charge terms(kT/qIc)(Cje+Cjc)For IBM SiGe NPN technology the last several terms are usually negligible since Re,Rc,and Rns are small190SiGe NPN Bipolar and fT versus CurrentvPlotted at left are the current gain and fT versus collector current for two different emitter width NPN transistorsBoth and fT drop off at high current density due to base push-out(called the Kirk Effect)vWhen the number of injected electrons exceeds the N type doping of the collector region,the base-collector space charge region pushes all the way to the heavily-doped N+subcollector.vThe use of a self-aligned collector pedestal N implant raises the doping in the intrinsic portion of the collector N epi and prevents base push-out until very high current(RC(in parallel)and is neglectedvWe can derive the small-signal gain due to the differential input by applying KVL to loop Ava(t)(-va(t)=2va(t)=ib1r1 ib2r2=2ib1r since ib1=-ib2 and r1=r2Or,ib1=va(t)/r and ib2=-va(t)/r R.W.KnepperSC412,slide 8-18195Bipolar Diff Amp with Differential Inputs(continued)vSolving for the output voltages we can obtainvo1=-ic1RC=-oib1RC=-(o/r)va(t)RC and v02=+(o/r)va(t)RC vWe can now find the gain with differential-mode input and single-ended output or with differential-mode input and differential outputAdm-se1=v01/vidm=-gmRC/2 and Adm-se2=+gmRC/2Adm-diff=(v01 v02)/vidm=-gmRCvSince corresponding currents on the left and right side of the differential small-signal model are always equal and opposite,implying that no current ever flows throw rnNode E acts as a“virtual ground”vIf the output resistances of Q1 and Q2 are low enough to require keeping them in the analysis,we simply replace RC with the parallel combination of RC|ro for transistor Q1 and Q2R.W.KnepperSC412,slide 8-19196Small-Signal Model of BJT Diff Amp with CM InputsvThe figure below is the small-signal model for the diff amp with common-mode inputsv1=v2=vb(t)and vicm=(v1+v2)=vb(t)vThe common-mode currents from both inputs flow through rn as shown by the two loops in=2(o+1)ib1=2(o+1)ib2and therefore,vb=ibr+2(o+1)ibrn or ib=vb/r+2(o+1)rnvThe collector voltages can be found asv01=v02=-oRCvb/r+2(o+1)rn=-gmRCvb/1+2gmrnvThe common-mode gain with single-ended output is given byAcm-se1=Acm-se2=vo1/vicm=vo2/vicm=-gmRC/1+2gmrn=-RC/2rnvThe common-mode gain with differential output is Acm-diff=(vo1 vo2)/vicm=0vDo Example 8.1,p.488R.W.KnepperSC412,slide 8-20197BJT Diff Amp Circuit with Both Diff&CM InputsvThe example below illustrates the principle of superposition in dealing with both differential mode and common mode inputs to a diff ampv1=vx cos 1t+vy sin 2t and v2=vx cos 1t vy sin 2tvUsing the definitions of differential mode and common mode inputs,respectively,vidm=v1 v2=2vy sin 2t and vicm=(v1+v2)/2=vx cos 1t,we can obtainvo1=Adm-se1 vidm+Acm-se1 vicm =-oRC(vy/r)sin 2t+(vx/r +2(o+1)rn)cos 1tThe expression for v02 is similar except that the first term(differential mode)has a minus signNote that the common mode output is reduced by the factor(o+1)in the denominatorR.W.KnepperSC412,slide 8-21198Common-Mode Rejection RatiovIn a differential amplifier we typically want to amplify the differential input while,at the same time,rejecting the common-mode input signalvA figure of merit Common Mode Rejection Ratio is defined asCMRR=|Adm|/|Acm|where Adm is the differential mode gain and Acm is the common mode gainvFor a bipolar diff amp with differential output,the CMRR is found to beCMRR=|Adm-diff|/|Acm-diff|=|-gmRC|/0=infinityvIn the case of the bipolar diff amp with single-ended output,CMRR is given byCMRR=|Adm-se|/|Acm-se|=|gmRC|/|oRC/r+2(o+1)rn|=r+2(o+1)rn/2r=orn/r=gmrn=ICrn/VT =Iorn/2 VT since o=gmr and VT is defined as kT/qvCMRR is often expressed in decibels,in which case the definition becomesCMRR=20 log(|Adm|/|Acm|)R.W.KnepperSC412,slide 8-22199BJT Diff Amp Input and Output ResistanceInput Resistance:vFor differential-mode inputs,the input resistance can be found asrin-dm=(v1 v2)/ib1=(va (-va)/(va/r)=2var/va=2r vFor common-mode inputs,the input resistance is quite differentrin-cm=(v1+v2)/ib1=vb/vb/(r+2(o+1)rn)=r+2(o+1)rnOutput Resistance:vFor differential outputs,we can use the test voltage method(below)for deriving the output resistance where all inputs are set to zeroSince ib1 and ib2 are both zero,we have itest=vtest/(RC+RC)=vtest/2RC or rout-diff=2RCvFor single-ended outputs,rout-se=RC|ro=RCR.W.KnepperSC412,slide 8-23200Bipolar Diff Amp Biasing ConsiderationsvA bipolar differential amplifier with ideal current source and resistor loads is shown vIt is assumed that components are matched sufficiently such that bias current Io is split evenly between the left and right-hand legsvNode E will take a voltage value such that IC1=IC2=Io/2 when v1=v2=0vBy using the Ebers-Moll dc model for the NPN transistors,we can determine the voltage at node EIE=IEO exp(qVBE/kT)1 =IEO exp(qVBE/kT)=Io/2or,VBE=(kT/q)ln(IE/IEO)Typically,VBE=0.75-0.85 V in modern NPN transistorsvIt is important to design RC such that vout never drops so low so as to force Q1 or Q2 into saturation.R.W.KnepperSC412,slide 8-24201BJT Diff Amp with Simple Resistor Current SourcevThe simplest approach to building a current source is with a resistorvGiven that node E is one VBE drop below GND,we can choose RE to provide the desired bias current IoRE=(0 VBE VEE)/IovPreventing saturation in Q1 and Q2 provides an upper bound for RCRC =50Common-mode,single-ended gain =0.2vCompleted design is shown abovevIn class Exercise:8.4,8.5,&8.6R.W.KnepperSC412,slide 8-26203BJT Diff Amp with BJT Current SourcevThe expression for common-mode gain on slide 8-20(-RC/2rn)shows that in order to reduce Acm,we want to make the effective impedance of the current source very highUsing a resistor to generate the current source limits our design options in making rn(RE in this case)highvAn alternate method of generating Io is to use an NPN transistor current source similar to that shown at the leftQ3 is an NPN biased in the forward active region so that rn(given by the inverse slope of the collector characteristics)is very highRA and RB form a voltage divider establishing VB=VEE x RA/(RA+RB)where VEE is VT,Vgs VT VdsvIds=N Vds(Vgs VT Vds/2)vinterface is inverted and not pinched off at drain(Fig.a)Pinch-off Point:Vgs VT,Vds=Vdsatvchannel pinches off at the drain junctionvsimple theory:Vdsat=Vgs VT(Fig.b)Saturated Region:Vgs VT,Vgs VT Vt,but increases to CoxW(L-2L)in the accumulation region.R.W.KnepperSC412,slide 8-39216MOSFET High Frequency Figures of MeritUnity gain bandwidth product fT(frequency where current gain falls to 1):vAssume that a small signal sinusoidal source vGS=Vpsin(t)is applied to the gateInput current is given by iG=CG(dvGS/dt)=CG Vpcos(t)=(Cgs+Cgd)Vpcos(t)Output current is given by iDS=gm vGS from the definition of gm If we write the magnitude of the ac current