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1、外文出處： Springer-Link電子期刊 附件1：外文資料翻譯譯文 SJA1000 獨立的CAN控制器應用指南 1 介紹 SJA1000是一個獨立的CAN控制器，它在汽車和普通的工業(yè)應用上有先進的特征。由于它和PCA82C200 在硬件和軟件都兼容，因此它將會替代PCA82C200。SJA1000有一系列先進的功能適合于多種應用，特別在系統(tǒng)優(yōu)化、診斷和維護方面非常重要。 本文是要指導用戶設計基于SJA1000 的完整的CAN節(jié)點。同時本文還提供典型的應用電路圖和編程的流程圖。 2 概述 SJA1000 獨立的CAN控制器有2個不同的操作模式： BasicCAN模式(和P

2、CA82C200）兼容 PeliCAN模式 BasicCAN模式是上電后默認的操作模式。因此，用PCA82C200開發(fā)的已有硬件和軟件可以直接在SJA1000上使用，而不用作任何修改。 PeliCAN模式是新的操作模式，它能夠處理所有CAN2.0B 規(guī)范的幀類型。而且它還提供一些增強功能使SJA1000能應用于更寬的領域。 CAN 節(jié)點結構 通常，每個CAN 模塊能夠被分成不同的功能塊。SJA1000使用[3] [4] [5]最優(yōu)化的CAN收發(fā)器連接到CAN 。收發(fā)器控制從CAN控制器到總線物理層或相反的邏輯電平信號。 上面一層是一個CAN 控制器，它執(zhí)行在CAN規(guī)范[8]里規(guī)定

3、的完整的CAN協(xié)議。它通常用于報文緩沖和驗收濾波，而所有這些CAN功能，都由一個模塊控制器控制它負責執(zhí)行應用的功能。例如，控制執(zhí)行器、讀傳感器和處理人機接口（MMI）。 如圖1所示，SJA1000獨立的CAN控制器通常位于微型控制器和收發(fā)器之間，大多數(shù)情況下這個控制器是一個集成電路。 　 　 圖1 CAN模塊裝置 2.2 結構圖 下圖是SJA1000 的結構圖 圖2 SJA1000的結構圖 根據(jù)CAN規(guī)范，CAN核心模塊控制CAN幀的發(fā)送和接收。 接口管理邏輯負責連接外部主控制器，該控制器可以是微型控制器或任何其他器件。經過SJA1000復用的地址/數(shù)據(jù)總線訪問寄

4、存器和控制讀/寫選通信號都在這里處理。另外，除了PCA82C200已有的BasicCAN功能，還加入了一個新的PeliCAN 功能。因此，附加的寄存器和邏輯電路主要在這塊里生效。 SJA1000的發(fā)送緩沖器能夠存儲一個完整的報文（擴展的或標準的）。當主控制器初始化發(fā)送，接口管理邏輯會使CAN 核心模塊從發(fā)送緩沖器讀CAN 報文。 當收到一個報文時，CAN核心模塊將串行位流轉換成用于驗收濾波器的并行數(shù)據(jù)。通過這個可編程的濾波器SJA1000 能確定主控制器要接收哪些報文。 所有收到的報文由驗收濾波器驗收并存儲在接收FIFO。儲存報文的多少由工作模式決定，而最多能存儲32個報文。因為數(shù)據(jù)超載

5、可能性被大大降低，這使用戶能更靈活地指定中斷服務和中斷優(yōu)先級。 3 系統(tǒng) 為了連接到主控制器，SJA1000提供一個復用的地址/數(shù)據(jù)總線和附加的讀/寫控制信號。SJA1000可以作為主控制器外圍存儲器映射的I/O器件。 3.1 SJA1000 的應用 SJA1000 的寄存器和管腳配置使它可以使用各種各樣集成或分立的CAN收發(fā)器。由于有不同的微控制器接口，應用可以使用不同的微控制器。 圖3所示是一個包括80C51微型控制器和PCA82C251收發(fā)器的典型SJA1000應用。CAN 控制器功能像是一個時鐘源，復位信號由外部復位電路產生。在這個例子里，SJA1000 的片選由微控制器的口

6、控制。否則，這個片選輸入必須接到VSS。它也可以通過地址譯碼器控制，例如，當?shù)刂?數(shù)據(jù)總線用于其他外圍器件的時侯。 圖3 典型的SJA1000應用 3.2 電源 SJA1000有三對電源引腳，用于CAN 控制器內部不同的數(shù)字和模擬模塊。 VDD1/VSS1：內部邏輯 （數(shù)字） VDD2/VSS2：輸入比較器 （模擬） VDD3/VSS3： 輸出驅動器 （模擬） 為了有更好的EME性能，電源應該分隔開來。例如為了抑制比較器的噪聲，VDD2 可以用一個RC濾波器來退耦。 3.3 復位 為了使SJA1000正確復位，CAN控制器的XTAL1管腳必須連接一個穩(wěn)定的振蕩器時鐘（見）

7、節(jié)。引腳17的外部復位信號要同步并被內部延長到15個tXTAL。這保證了SJA1000 所有寄存器能夠正確復位（見[1] ）。要注意的是上電后的振蕩器的起振時間必須要考慮。 3.4 振蕩器和時鐘策略 SJA1000能用片內振蕩器或片外時鐘源工作。另外CLKOUT管腳可被使能，向主控制器輸出時鐘頻率。圖4顯示了SJA1000應用的四個不同的定時原理。如果不需要CLKOUT信號，可以通過置位時鐘分頻寄存器（Clock Off=1）關斷。這將改善CAN節(jié)點的EME性能。CLKOUT信號的頻率可以通過時鐘分頻寄存器改變： fCLKOUT = fXTAL / 時鐘分頻因子（1，2，4，6，8 ，1

8、0 ，12 ，14）。 上電或硬件復位后，時鐘分頻因子的默認值由所選的接口模式（引腳11）決定。如果使用16MHz的晶振，Intel 模式下CLKOUT 的頻率是8 MHz， Motorola 模式中復位后的時鐘分頻因子是12，這種情況CLKOUT會產生的頻率。 圖4 時鐘策略 睡眠和喚醒 置位命令寄存器的進入睡眠位（BasicCAN ）模式或模式寄存器（PeliCAN模式）的睡眠模式位后，如果沒有總線活動和中斷等待，SJA1000就會進入睡眠模式。振蕩器在15個CAN位時間內保持運行狀態(tài)。此時,微型控制器用CLKOUT頻率來計時，進入自己的低功耗模式。如果出現(xiàn)三個喚醒條件之中的

9、一個[1]，振蕩器會再次啟動并產生一個喚醒中斷。振蕩器穩(wěn)定后，CLKOUT頻率被激活。 3.5 CPU接口 SJA1000支持直接連接到兩個著名的微型控制器系列：80C51和68xx。通過SJA1000的MODE引腳可選擇接口模式： Intel模式： MODE 高 Motorola模式： MODE 低 地址/數(shù)據(jù)總線和讀/寫控制信號在Intel模式和Motorola模式的連接如圖5所示。Philips基于80C51系列的8位微控制器和XA結構的16位微型控制器都使用Intel 模式。 為了和其他控制器的地址數(shù)據(jù)總線和控制信號匹配，必須要附加邏輯電路。但是必須確保在上電期間不產生寫

10、脈沖。另一個方法在這個時候使片選輸入是高電平，禁能CAN 控制器。 圖5 SJA1000的CPU時鐘接口 3.6 物理層接口 為了和PCA82C200兼容,SJA1000包括一個模擬接收輸入比較器電路。如果收發(fā)器的功能由分立元件實現(xiàn)，就要用到這個集成的比較器。 圖6 SJA1000的接收輸入比較器 如果使用外部集成收發(fā)器電路，而且沒有在時鐘分頻寄存器里使能比較器旁路功能，RX1輸出要被連接到2.5V 的參考電壓（現(xiàn)有的收發(fā)器電路參考電壓輸出）。圖6顯示了兩種設置的相應電路：CBP=激活和CBP=非激活另外喚醒信號的通道被下拉對于使用集成的收發(fā)器電路的所有新應用我們建議

11、激活（使用）SJA1000的比較器旁路功能（圖7）。如果這個功能被使能，施密特觸發(fā)器的輸入有效，內部的傳 播延遲tD2比接收比較器的延遲tD1要小得多。它對最大的總線長度[6]有正面的影響。另外，休眠模式的電流將顯著降低。 圖7 帶有集成收發(fā)器電路的標準應用 附件2：外文原文（復印件） SJA1000 Stand-alone CAN controller 1. INTRODUCTION The SJA1000 is a stand-alone CAN Controller product with advanced features for use in

12、 automotive and general industrial applications. It is intended to replace the PCA82C200 because it is hardware and software compatible. Due to an enhanced set of functions this device is well suited for many applications especially when system optimization, diagnosis and maintenance are important.

13、 This report is intended to guide the user in designing complete CAN nodes based on the SJA1000. The report provides typical application circuit diagrams and flow charts for programming. 2. OVERVIEW The stand-alone CAN controller SJA1000 [1] has two different Modes of Operation: - BasicCAN Mode (

14、PCA82C200 compatible) - PeliCAN Mode Upon Power-up the BasicCAN Mode is the default mode of operation. Consequently, existing hardware and software developed for the PCA82C200 can be used without any change. In addition to the functions known from the PCA82C200 [7], some extra features have been i

15、mplemented in this mode which make the device more attractive. However, they do not influence the compatibility to the PCA82C200. The PeliCAN Mode is a new mode of operation which is able to handle all frame types according to CAN specification 2.0B [8]. Furthermore it provides a couple of enhanced

16、 features which makes the SJA1000 suitable for a wide range of applications. 2.1 CAN Node Architecture Generally each CAN module can be divided into different functional blocks. The connection to the CAN bus lines is usually built with a CAN Transceiver optimized for the applications [3], [4], [5]

17、. The transceiver controls the logic level signals from the CAN controller into the physical levels on the bus and vice versa. The next upper level is a CAN Controller which implements the complete CAN protocol defined in the CAN Specification [8]. Often it also covers message buffering and accepta

18、nce filtering. All these CAN functions are controlled by a Module Controller which performs the functionality of the application. For example, it controls actuators, reads sensors and handles the man-machine interface (MMI). As shown in Figure 1 the SJA1000 stand-alone CAN controller is always loc

19、ated between a microcontroller and the transceiver, which is an integrated circuit in most cases. 2.2 Block Diagram The following figure shows the block diagram of the SJA1000. The CAN Core Block controls the transmission and reception of CAN frames according to the CAN specification. The I

20、nterface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access via the SJA1000 multiplexed address/data bus and controlling of the read/write strobes is handled in this unit. Additionally to the BasicCAN funct

21、ions known from the PCA82C200, new PeliCAN features have been added. As a consequence of this, additional registers and logic have been implemented mainly in this block. The Transmit Buffer of the SJA1000 is able to store one complete message (Extended or Standard). Whenever a transmission is initi

22、ated by the host controller the Interface Management Logic forces the CAN Core Block to read the CAN message from the Transmit Buffer. When receiving a message, the CAN Core Block converts the serial bit stream into parallel data for the Acceptance Filter. With this programmable filter the SJA1000

23、decides which messages actually are received by the host controller. All received messages accepted by the acceptance filter are stored within a Receive FIFO. Depending on the mode of operation and the data length up to 32 messages can be stored. This enables the user to be more flexible when speci

24、fying interrupt services and interrupt priorities for the system because the probability of data overrun conditions is reduced extremely. 3. SYSTEM For connection to the host controller, the SJA1000 provides a multiplexed address/data bus and additional read/write control signals. Th

25、e SJA1000 could be seen as a peripheral memory mapped I/O device for the host controller. 3.1 SJA1000 Application Configuration Registers and pins of the SJA1000 allow to use all kinds of integrated or discrete CAN transceivers. Due to the flexible microcontroller interface applications with diffe

26、rent microcontrollers are possible. In Figure 3 a typical SJA1000 application diagram including 80C51 microcontroller and PCA82C251 transceiver is shown. The CAN controller functions as a clock source and the reset signal is generated by an external reset circuitry. In this example the chip select

27、of the SJA1000 is controlled by the microcontroller port function P2.7. Instead of this, the chip select input could be tied to VSS. Control via an address decoder is possible, e.g., when the address/data bus is used for other peripherals. 3.2 Power Supply The SJA1000 has three pairs of voltage

28、supply pins which are used for different digital and analog internal blocks of the CAN controller. VDD1 / VSS1: internal logic (digital) VDD2 / VSS2: input comparator (analog) VDD3 / VSS3: output driver (analog) The supply has been separated for better EME behaviour. For instance the VDD2 can be

29、 de-coupled via an RC 3.3 Reset For a proper reset of the SJA1000 a stable oscillator clock has to be provided at XTAL1 of the CAN controller, see also chapter 3.4. An external reset on pin 17 is synchronized and internally lengthened to 15 . This guarantees a correct reset of all SJA1000 register

30、s (see [1]). Note that an oscillator start-up time has to be taken into account upon power-up. 3.4 Oscillator and Clocking Strategy The SJA1000 can operate with the on-chip oscillator or with external clock sources. Additionally the CLK OUT pin can be enabled to output the clock frequency for the

31、host controller. Figure 4 shows four different clocking principles for applications with the SJA1000. If the CLK OUT signal is not needed, it can be switched off with the Clock Divider register (Clock Off = 1). This will improve the EME performance of the CAN node. The frequency of the CLK OUT sign

32、al can be changed with the Clock Divider Register: f CLK OUT = f XTAL / Clock Divider factor (1,2,4,6,8,10,12,14). Upon power up or hardware reset the default value for the Clock Divider factor depends on the selected interface mode (pin 11). If a 16 MHz crystal is used in Intel mode, the frequenc

33、y at CLK OUT is 8 MHz. In Motorola mode a Clock Divider factor of 12 is used upon reset which results in 1,33 MHz in this case. Sleep and Wake-up Upon setting the Go To Sleep bit in the Command Register (BasicCAN mode) or the Sleep Mode bit in the Mode Register (PeliCAN mode) the SJA1000 w

34、ill enter Sleep Mode if there is no bus activity and no interrupt is pending. The oscillator keeps on running until 15 CAN bit times have been passed. This allows a microcontroller clocked with the CLK OUT frequency to enter its own low power consumption mode. If one of three possible wake-up condi

35、tions [1] occurs the oscillator is started again and a Wake-up interrupt is generated. As soon as the oscillator is stable the CLK OUT frequency is active. 3.5 CPU Interface The SJA1000 supports the direct connection to two famous microcontroller families: 80C51 and 68xx. With the MODE pin of the

36、SJA1000 the interface mode is selected. Intel Mode: MODE = high Motorola Mode: MODE = low The connection for the address/data bus and the read/write control signals in both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers based on the 80C51 family and the 16-bit mi

37、crocontrollers with XA architecture the Intel Mode is used. For other controllers additional glue logic is necessary for adaptation of the address/data bus and the control signals. However, it has to be made sure that no write pulses are generated during power-up. Another possibility is to disable

38、the CAN controller with a high-level on the chip select input in this time. 3.6 Physical Layer Interface For compatibility purposes with the PCA82C200, the SJA1000 includes an analog receive input comparator circuit. This integrated comparator can be used if the transceiver function is realized

39、with discrete components. If an external integrated transceiver circuit is used and the comparator bypass function is not enabled in the Clock Divider Register, the RX1 input has to be connected to a reference voltage of 2.5V (reference voltage output of existing transceiver circuits). Figure 6

40、 shows the equivalent circuits for both configurations: CBP = active and CBP = inactive. Additionally the path for the wake-up signal is drawn. For all new applications where an integrated transceiver circuit is used, it is recommended to activate the comparator bypass function of the SJA1000 (Figur

41、e 7). If this function is enabled, a schmitt-trigger input is used and the internal propagation delay tD2 is much shorter as the delay tD1. of the receive comparator. This has a positive impact on the maximum bus length [6]. Additionally, it will reduce the supply current in sleep mode significantly.