19、en
temp<=temp+1;
else
temp<="0000";
clko<=not clko;
end if;end if;
end process;
end a;
正弦函數模塊
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sin is
port(clk4:in std_logic;
k::
20、in integer range 15 downto 0;
dd4:out integer range 255 downto 0);
end sin;
architecture dacc of sin is
signal q: integer range 63 downto 0;
begin
process(clk4)
begin
if (clk4'event and clk4='1') then
q<=q+k;
end if;
21、
end process;
process(q)
begin
case q is
when 00=>dd4<=255;
when 01=>dd4<=254;
when 02=>dd4<=253; when 36=>dd4<=10;
when 03=>dd4<=250; when 37=>dd4<=15;
when 04=>dd4<=245;
22、when 41=>dd4<=47;
when 05=>dd4<=240; when 38=>dd4<=21;
when 06=>dd4<=234; when 39=>dd4<=29;
when 07=>dd4<=226; when 40=>dd4<=37;
when 08=>dd4<=218; when 41=>dd4<=47;
when 09=>dd4<=208; when 42=>dd4<=57;
when 10=>dd
23、4<=198; when 43=>dd4<=67;
when 11=>dd4<=188; when 44=>dd4<=79;
when 12=>dd4<=176; when 45=>dd4<=90;
when 13=>dd4<=165; when 46=>dd4<=103;
when 14=>dd4<=152; when 47=>dd4<=115;
when 15=>dd4<=140; when
24、 48=>dd4<=128
when 16=>dd4<=128; when 49=>dd4<=140;
when 17=>dd4<=115; when 50=>dd4<=165;
when 18=>dd4<=103; when 51=>dd4<=176;
when 19=>dd4<=90; when 52=>dd4<=188;
when 20=>dd4<=79; when 53=>dd4<=198;
when 21=>d
25、d4<=67; when 54=>dd4<=208;
when 22=>dd4<=57; when 55=>dd4<=218;
when 23=>dd4<=47; when 56=>dd4<=226;
when 24=>dd4<=37; when 57=>dd4<=234;
when 25=>dd4<=29; when 58=>dd4<=240;
when 26=>dd4<=21;
26、when 59=>dd4<=245;
when 27=>dd4<=15; when 60=>dd4<=250;
when 28=>dd4<=10; when 61=>dd4<=253;
when 29=>dd4<=5; when 62=>dd4<=254;
when 30=>dd4<=2; when 63=>dd4<=255;
when 31=>dd4<=1; when 63=>dd4<=255;
when
27、32=>dd4<=0; when others=>null;
when 33=>dd4<=1; end case;
when 34=>dd4<=2; end process;
when 35=>dd4<=5; end dacc;
三角波
library ieee;
use ieee.std_logic_1164.al
28、l;
use ieee.std_logic_unsigned.all;
entity tria is
port(clk3:in std_logic;
k:in integer range 15 downto 0;
dd3:out integer range 255 downto 0);
end tria;
architecture dacc of tria is
signal b:std_logic;
signal c:integer range 255 downto 0;
begin
process(clk3)
begin
if
29、(clk3'event and clk3='1') then
if(b='0') then
c<=c+k;
if(c>=250) then
b<='1';
end if;
elsif(b='1') then
c<=c-k;
if(c<=1) then
b<='0';
end if;
end if;
dd3<=c;
end if;
end process;
end dacc;
方波
30、
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity square is
port(clk1 : in std_logic;
k:in integer range 15 downto 0;
dd1 : buffer integer range 255 downto 0);
end square;
architecture dacc of square is
31、
signal q: integer range 255 downto 0;
begin
process(clk1)
begin
if (clk1'event and clk1='1') then
q<=q+k;
end if;
end process;
process(q)
begin
case q is
when 0 to 127=>dd1<=255;
when 128 to 255=>dd1<=127;
when others=>null;
end case;
end process;
end dac
32、c;
特殊波形
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sintra is
port(clk4:in std_logic;
k:in integer range 15 downto 0;
dd4:out integ
33、er range 255 downto 0);
end sintra;
architecture dacc of sintra is
signal q: integer range 63 downto 0;
begin
process(clk4)
begin
if (clk4'event and clk4='1') then
q<=q+k;
end if;
end process;
process(q)
begin
case q is
when 00=>dd4<=255;
when 01=>dd4<
34、=254;
when 02=>dd4<=253; when 36=>dd4<=10;
when 03=>dd4<=250; when 37=>dd4<=15;
when 04=>dd4<=245; when 41=>dd4<=47;
when 05=>dd4<=240; when 38=>dd4<=21;
when 06=>dd4<=234; when 39=>
35、dd4<=29;
when 07=>dd4<=226; when 40=>dd4<=37;
when 08=>dd4<=218; when 41=>dd4<=47;
when 09=>dd4<=208; when 42=>dd4<=57;
when 10=>dd4<=198; when 43=>dd4<=67;
when 11=>dd4<=188; when 44=>dd4<=79;
when 12=>dd4<=176;
36、 when 45=>dd4<=90;
when 13=>dd4<=165; when 46=>dd4<=103;
when 14=>dd4<=152; when 47=>dd4<=115;
when 15=>dd4<=140; when 48=>dd4<=128
when 16=>dd4<=128; when 49=>dd4<=140;
when 17=>dd4<=115; when 50=>dd4
37、<=165;
when 18=>dd4<=103; when 51=>dd4<=176;
when 19=>dd4<=90; when 52=>dd4<=188;
when 20=>dd4<=79; when 53=>dd4<=198;
when 21=>dd4<=67; when 54=>dd4<=208;
when 22=>dd4<=57; when 55=>dd4<=218;
when 23=>dd4<=47;
38、 when 56=>dd4<=226;
when 24=>dd4<=37; when 57=>dd4<=234;
when 25=>dd4<=29; when 58=>dd4<=240;
when 26=>dd4<=21; when 59=>dd4<=245;
when 27=>dd4<=15; when 60=>dd4<=250;
when 28=>dd4<=10; when 61
39、=>dd4<=253;
when 29=>dd4<=5; when 62=>dd4<=254;
when 30=>dd4<=2; when 63=>dd4<=255;
when 31=>dd4<=1; when 63=>dd4<=255;
when 32=>dd4<=0; when others=>null;
when 33=>dd4<=1; end case;
when 34=>dd4<=2;
40、 end process;
when 35=>dd4<=5; end dacc;
分頻1Hz
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp1HZ IS
PORT(clk:in std_logic; --10M
clk1Hz: buffer STD_LOGIC);
41、
END fp1hz;
ARCHITECTURE one OF fp1hz IS
SIGNAL test: integer range 0 to 6000000;
begin
process(clk)
begin
if clk'event and clk='1' then
if test<5000000 then
test<=test+1;
else
test<=0;
clk1hz<=not clk1hz;
end if;
end if;
end process;
end one;
測頻模塊
LIBRA
42、RY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY freq IS
PORT(fsin: in STD_LOGIC;
clk: IN STD_LOGIC;
dout0,dout1,dout2,dout3: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END freq;
ARCHITECTURE one OF freq IS
SIGNAL test_en: STD_LOGIC;
SIGNAL
43、clear: STD_LOGIC;
SIGNAL data: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN test_en<=NOT test_en;
END IF;
END PROCESS;
clear<=NOT clk AND NOT test_en;
PROCESS(fsin)
BEGIN
IF clear='1' THEN data<="0000";
ELSIF fsin'ev
44、ent AND fsin='0'
THEN
IF data(15 DOWNtO 0)="1001"
THEN data<=data+"0111";
elsIF data(11 DOWNtO 0)=""
THEN data<=data+"";
ELSIF data(7 DOWNTO 0)="10011001"
THEN data<=data+"01100111";
ELSIF data(3 DOWNTO 0)="1001"
THEN data<=data+"0111";
ELSE data<=data+1;
45、 END IF;
END IF;
END PROCESS;
PROCESS(test_en,data)
BEGIN
IF test_en'event AND test_en='0' THEN
dout0<=data(3 downto 0);
dout1<=data(7 downto 4);
dout2<=data(11 downto 8);
dout3<=data(15 downto 12);
END IF;
46、 END PROCESS;
END one;
控制模塊
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all
entity control is
port(sel:in std_logic_vector(1 downto 0);
k0,k1,k2,k3:in integer range 255 downto 0;
qout:out i
47、nteger range 255 downto 0);
end control;
architecture a of control is
begin
process(sel,k0,k1,k2,k3)
begin
if sel=“00” then
qout<=k0;
elsif sel=“01” then
qout<=k1;
elsif sel=“10” then
qout<=k2;
elsif se
48、l=“11” then
qout<=k3;
end if;
end process;
end a;
3.4 電路模塊組成及引腳設置
3.4.1路模塊組成
3.4.2引腳設置
3.5 硬件實現(xiàn)及調試結果
下載編譯成功后，定義芯片管腳，開關K1、K2、K3控制分頻系數，K14、K15為Sel選擇信號，Sel=00時為正弦波，Sel=01時為三角波，Sel=10時為方波，Sel=11時為特殊波形。將示波器連接到硬件上，觀察輸出波形。
第四章 課程設計總
49、結
通過這次課程設計，我受益匪淺。我們不僅鞏固了課上學到的知識，提高了我們實際動手的能力，而且了解到理論聯(lián)系實際和團結協(xié)作的重要性。同時我們也意識到在以后的學習和生活中要始終保持一絲不茍的態(tài)度，杜絕馬虎的態(tài)度，只有理論知識是遠遠不夠的，只有把所學的理論知識與實踐相結合起來，從理論中得出結論，才能真正為社會服務，從而提高自己的實際動手能力和獨立思考的能力。在設計的過程中遇到問題，可以說得是困難重重，這畢竟第一次做的，難免會遇到過各種各樣的問題，同時在設計的過程中發(fā)現(xiàn)了自己的不足之處，對以前所學過的知識理解得不夠深刻，掌握得不夠牢固。
通過本次設計，增加自己的理論知識，系統(tǒng)的了解了波形發(fā)生器的
50、設計流程，尤其是硬、軟件的設計方法，掌握了波形發(fā)生器的基本功能及編程方法，掌握了它的一般原理，也進一步掌握了QuartusⅡ的使用。而且也開拓了思路，鍛煉了實踐動手能力，提高了分工協(xié)作能力和分析問題，解決問題的能力，達到了本次課程設計的目的。
此次任意波形發(fā)生器的設計,給我留下深刻的印象。我會在以后的學習、生活中磨練自己，使自己能夠滿足社會的需求。同時，我非常感謝張老師的指導，在她的細心講解下，我順利的完成的此次任意波形發(fā)生器的課程設計。
參考文獻
[1] 江國強 EDA技術與應用 北京：電子工業(yè)出版社，2005
[2]孫加存 電子設計自動化 西安：西安電子科技大學出版社 2008
[3] 林明權，等 VHDL數字控制系統(tǒng)設計范例 北京：電子工業(yè)出版社，2005
[4] 焦素敏 EDA應用技術 北京：清華大學出版社，2005
[5] 王振紅 VHDL數字電路設計與應用實踐教程 北京：機械工業(yè)出版社，2003
EDA課程設計副本
